The Impact of Analog-to-Digital Converter Architecture and Variability on Analog Neural Network Accuracy

The analog-to-digital converter (ADC) is a key component in analog in-memory computing accelerators, but also bottleneck for the efficiency and accuracy of these systems. While trade-offs between power consumption, latency, area ADC design are well studied, it relatively unknown which implementations optimal algorithmic accuracy, particularly neural network inference. We explore space with focus on investigating sensitivity outputs to variability inside how this depends architecture. Compact models pipeline, cyclic, successive-approximation-register (SAR) ramp ADCs developed, used system-level simulation Our results show complex image recognition benchmark (ResNet50 ImageNet) capacitance mismatch, comparator offset, effective number bits (ENOB) each four architectures. find that robustness variations strongly design, inference sensitive value-dependent error characteristics cannot be captured by conventional ENOB precision metric.